SystemVerilog

Design and Verification of a SPI to JTAG Interface Adapter

Goal and Motivation: Almost all hardware devices have JTAG connections which can provide data from registers or provide low level control of pins via a boundary scan chain. Unfortunately, most microcontrollers do not have libraries or drivers for communicating using the JTAG protocol. The goal of this project is to provide a way to allow users to use existing libraries to access data that is typically accessed via JTAG protocol.

SDSU-EE492-Advanced Digital Hardware Design

Hardware Integrated Prototyping Environment

HIPE provides an interface between the user’s simulation environment and a Field Programmable Gate Array (FPGA) containing a Design Under Test (DUT).

SDSU-EE465-Senior Design

Communication Protocols for Embedded Systems